For the last several years NAND flash cells have been getting smaller and smaller. Cells have gone from storing a single bit to three bits in an effort to pack more data into the same amount of space. The smaller the cell and the more data in can hold the cheaper flash becomes, right? We all know that the more data we pack into a cell the fewer times we can write new data to said cell. This is due to a phenomenon known as quantum tunneling. This phenomenon causes a physical breakdown of a part of the memory cell. While software may allow us to add a fourth bit or more at some point we will likely hit a wall. At the same time an individual NAND cell has shrunk far smaller than ever before. While we haven’t reached a technical wall in how much smaller they can go we have ran into a complexity wall.
If we can no longer shrink our NAND cells or add more data to each cell then we need to find another way to increase density. Density equals lower cost in flash storage so something needs to change. One thing that has recently began to happen is we’ve moved from planar or 2D NAND to 3D or vertical NAND. Basically we’ve started to turn and stack cells in an even more efficient way which will allows for greater density. Doing this is simply a bandage as the underlying problem is not addressed.
In order for storage to move forward and continue to grow in capacities and shrink in price an alternative to NAND flash needs to be developed. Many companies have been working on this problem for years, several even bringing products to market with limited success. As research into these alternatives continues it’s just a matter of time before a NAND replacement starts to gain market share. There are 5 major types of memory cells being developed as possible replacements for NAND, each with strengths and weaknesses. They are phase change memory, resistive RAM, Magnetoresistive RAM, Ferroelectric RAM, and spin-transfer torque RAM.
Phase Change Memory (PCM) is one of the more interesting emerging types of non-volatile memory entering the market today. While this is not exactly a new technology it has not yet achieved mainstream success. In current memory technologies data is stored as either a 0 or 1 in a transistor. PCM does not use transistors for data storage, but instead uses a material which can be either amorphous or crystalline to determine the bit cell state. A diode is used to conduct electric current into the material to measure resistance. When the electric resistance is high the material is in an amorphous state which is a “0” or empty state. When a write occurs unidirectional electric currents are sent into the material causing it to literally stiffen into its crystalline state. When the data is deleted the material is melted using the heat of the electric current and returned it its amorphous state.
Phase Change Memory has several challenges which need to be addressed. The high programming current density may limit scalability. While endurance of PCM is significantly better than that of NAND, it is limited by the physical limitations of the bit cell material. Over time the material will experience threshold voltage drift making it harder to distinguish between the two states.
Resistive random-access memory, also called RRAM or ReRAM, is similar to Phase Change Memory in that resistance is again being measured. The basic design of an RRAM cell is some type of dielectric material which has thermal or ionic properties which allow for a change in its resistance under electric current. This type of ability is known as resistive switching and is completely non-volatile and reversible. Much like a capacitor this dielectric is sandwiched between two electric conductors know as electrodes. The RRAM cell stores data based on the directional motion of the ions inside the resistive switching medium. Many types of materials may be used for this design but the one gaining most traction is called the platinum sandwich where silicon oxide is sandwiched between platinum to form the RRAM cell.
RRAM is very energy efficient; however the tradeoff is in terms of loss of performance. One of the biggest challenges facing RRAM is that of the current leakage which may limit scalability; however several vendors are addressing this problem. RRAM is a very interesting technology and is likely to come to market fairly quickly.
MRAM, or Magnetoresistive random-access memory, is yet another in a class of memories which measures resistance to determine state within a cell. Similar to DRAM in concept a MRAM cell uses charges to store state data. DRAN uses electrical charges whereas MRAM uses magnetic charges. A Magnetoresistive material is one which shows a change in electric resistance when placed in a magnetic field. The cell is made up of an insulating material sandwiched between two ferromagnetic places. The bottom piece of the sandwich is pinned to specific polarity while the top piece’s polarity can be changed. The top piece, also known as the free layer, changes polarity when a current is passed. This creates a magnetic field due to an effect known as the magnetic tunnel effect; which allows electrons to jump from the bottom to the top. This requires a fairly high electrical current to effect this polarity change. The state of the cell is determined by a difference in electric resistance based on polarity of the free layer.
The high current required to write data to a MRAM cell may limit the size an individual cell may shrink to. The size of the magnetic field generated is directly related to the size of the electrical current. As the cell shrinks the size of the electric current does not. This problem, known as half-select or write disturb, may mean MRAM cells have to remain fairly large and limiting the possible density.
Ferroelectric RAM, also known as FRAM or FeRAM, is very similar to DRAM in construction, but instead uses a ferroelectric capacitor. This capacitor uses a material which has a natural ability allowing the polarity to be reversed when exposed to an electric field. Reading state in this type of FRAM cell is done in a very unique manner. The transistor forces the cell into a “0” or un-programed state. If the cell was not already in the “0” state the polarity will reverse and cause an electric current to be outputted. If the cell is already in the “0” state no change will be detected. In this respect, reading from a FeRAM cell is a destructive process and any erased state cause by the read must be reprogrammed. This constant destroying of states to access data will eventually lead to wear our and may be the Achilles heel of FeRAM.
Spin-transfer torque memory, or STT-RAM, is actually a form or MRAM with a different method for causing the free layer to switch polarity. STT-RAM seeks to solve the problem of power consumption caused in classic MRAM cells by using a method requiring smaller electrical charges. Rather than using a magnetic field to switch the polarity of the free layer STT-RAM, it uses the directional spin of an electron to cause the same effect. Electrons have an intrinsic amount of angular momentum – meaning they spin either up or down naturally. In a normal electrical current 50% of the electrons spin up while the others spin down. By passing an electrical charge through the magnetically charged fixed layer, the free layer flips direction. A STT-RAM design is very similar to MRAM with the exception of the tunnel barrier now being metallic rather than insulating.
Each possible NAND replacement is currently in development by several manufacturers. While it’s impossible to tell which will eventually replace NAND, we can speculate as to which will come to market quickest. Phase Change Memory is already in a very limited market, but will likely be the quickest to push and replace NAND since extensive research already exists on the underlying technology. On the other hand, the spin-transfer torque memory uses a phenomenon which we have a limited understanding of today. As such, it is possible it will never make it to market if the promises of other technologies work out. Either way it is clear we have several strong options for replacing NAND in the future which will allow for better performance in a smaller amount of space.